Analysis of Chip Electronic Components’ Typical Yield in Taping Process Based on Virtual Metrology

This study addresses virtual metrology for the taping process of chip electronic components, in which partial observability, unmeasured disturbances, and severe label imbalance make direct batch-wise yield prediction unstable. Rather than proposing a new standalone learning algorithm, we develop a data-centric VM framework that reformulates the task as the prediction of operating-condition-level typical yield. First, physically relevant features are retained based on process knowledge and analyzed using Pearson correlation, Spearman correlation, and mutual information. We then perform multidimensional equal-frequency binning to partition the observable feature space into locally homogeneous operating condition groups, and define the within-bin median yield as the typical yield, thereby constructing an operating condition dictionary. Based on this dictionary-based representation, low-yield-oriented sample weighting is combined with nested cross-validation and Bayesian optimization for model comparison and hyperparameter tuning. Using desensitized production data from an electronic component taping process, the results under this representation show more stable prediction than direct modeling on unbinned batch samples while also improving tail-oriented fitting relative to unweighted baselines. These findings suggest that, for partially observable manufacturing data, operating condition stratification provides a practical basis for stabilizing VM prediction, while low-yield-oriented sample weighting further improves sensitivity to the low-yield tail, supporting picture yield early warning and process-level decision making.