RADI: A High-Performance Reconfigurable Array-Based Accelerator for DNN Implementations

Deep neural networks (DNNs) have gained significant attention due to the rapid growth of learning-based applications. However, the computational demands of DNNs limit their performance in many of these applications. As a result, extensive research has focused on hardware implementations of these networks as accelerators. Array-based accelerators are an efficient architecture type that employs an array of processing elements (PEs) for parallel computations. However, array-based accelerators cannot reach their potential performance due to having fixed dimensions to execute different layers of DNNs. This article proposes a reconfigurable architecture to address this limitation by adaptively selecting the size of PEs to better align with the dimensions of the active DNN layers. Simulations demonstrate significant improvements for various DNN models compared to state-of-the-art architectures. Experimental results show that the proposed architecture achieves, on average, 43% higher speed, 32% more resource utilization, and a 38% reduction in on-chip memory access rate compared to the baseline architecture when executing GoogLeNet model layers. These enhancements are achieved with only a 1.6% area overhead, making the proposed architecture a cost-effective design. Furthermore, by incorporating multithreading into the simulator's source code, we significantly accelerate simulations compared to the basic version.