Design and characterization of 16-bit single-poly EEPROM arrays in a 0.18-μm BCD process for PMIC applications

This paper presents the design and characterization of two 16-bit (4×4) single-poly EEPROM arrays based on different 4T memory cell architectures fabricated in a 0.18-μm BCD process for power management IC applications. Both memory cells employ Fowler–Nordheim tunneling for program and erase operations and are fully compatible with the baseline BCD process without additional masks. The 4T-Inv array provides rail-to-rail voltage readout with low static current and supports simultaneous readout of all 16 cells, while the 4T-Sel array offers current-mode sensing with a compact array implementation. Experimental results demonstrate stable array-level operation, endurance over 1000 program/erase cycles, and acceptable retention at 150 °C.