A Novel Standard Cell Structure and Physical Design Methodology to Enhance Routability

In the era of highly integrated circuits, continuous miniaturization has significantly increased routing complexity, thereby directly impacting circuit performance. As process scaling advances and the number of on-chip metal layers increases, conventional standard cell libraries face limitations that cause severe routing bottlenecks. To overcome these limitations, this paper proposes a dual-component approach. First, we introduce a novel standard cell structure that improves routing flexibility by expanding the degrees of freedom for pin access, particularly in highly congested regions. Second, we present a physical design methodology specifically designed to ensure seamless integration with existing electronic design automation (EDA) tools, allowing new cells to be effectively placed and routed without major modifications to current flows. The proposed approach was validated using the open-source ASAP7 process design kit (PDK). Experimental results confirm significant reductions in via count and total wirelength, leading to improved routability, reduced power consumption, and enhanced performance. These findings demonstrate that combining the new cell architecture with a tailored design methodology provides a practical alternative to conventional solutions, enabling more efficient and scalable circuit designs for future technology nodes.