Wear-Aware Routing Algorithm for Network-on-Chip Interconnects Using Linear Approximate Reinforcement Learning

As chip multiprocessors scale, the reliability of Network-on-Chip (NoC) interconnects becomes increasingly critical due to aging mechanisms such as electromigration (EM) and hot-carrier injection (HCI), which are strongly influenced by traffic-induced switching activity and temperature. Conventional routing algorithms, such as dimension-order routing (DOR), are oblivious to these effects and can lead to uneven stress distribution and premature failure of network components. This work presents a reinforcement learning (RL)-based adaptive routing framework that incorporates aging awareness directly into routing decisions. Each router operates as a distributed RL agent using linear function approximation, where EM and HCI based mean time to failure (MTTF) estimates are integrated into the feature representation and reward function. The proposed approach is evaluated using the gem5 Garnet cycle-accurate simulator on an 8×8 mesh across multiple synthetic traffic patterns, and is compared against both DOR and the state-ofthe- art aging-aware Clotho routing scheme. Results show that the RL-based approach achieves up to ∼ 5× improvement in EM lifetime and consistent gains in HCI lifetime compared to DOR. Compared to Clotho, the proposed method achieves improved reliability under several structured traffic patterns, while maintaining competitive packet latency across all evaluated scenarios. This work highlights the potential of reinforcement learning as a scalable and flexible framework for reliability-aware packet routing in NoC.