PulseExploreJournal ClubDebatesTrendingResearchersJournals
Instagram
HomeExploreJournal ClubTrending
Synapse
⌘+K
Synapse
February 1, 2017116 citations

9 A 1ms high-speed vision chip with 3D-stacked 140GOPS column-parallel PEs for spatio-temporal image processing

View Full Paper
TYTomohiro YamazakiHKHironobu KatayamaSUShuji Uehara

Key Points

Key points are not available for this paper at this time.

Abstract

High-speed vision systems that combine high-frame-rate imaging and highly parallel signal processing enable instantaneous visual feedback to rapidly control machines over human-visual-recognition speeds. Such systems also enable a reduction in circuit scale by using a fast and simple algorithm optimized for high-frame-rate processing 1. Previous studies on vision systems and chips 1-4 have yielded low imaging performance due to large matrix-based processing element (PE) parallelization 1-3, and low functionality of the limited-purpose column-parallel PE architecture 4, constraining vision-chip applications.

Ask AI
Helpful
Bookmark
Share
View Full Paper

Cite This Study

Yamazaki et al. (2017) studied this question.

synapsesocial.com/papers/6a010dd22ff633f3657834dfhttps://doi.org/10.1109/isscc.2017.7870271
Ask AI
Helpful
Bookmark
Share
View Full Paper