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May 13, 2026Electronics0 citationsOpen Access

Lightweight Hardware Implementation of a State of Charge Estimation Algorithm Using a Piecewise OCV–SOC Model

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GJGahyeon JangSKSeungbum KangSLS W Lee

Key Points

  • This study aims to develop a lightweight algorithm for estimating the state of charge in lithium-ion batteries to improve battery management systems.
  • Developed a piecewise OCV-SOC model for lithium-ion battery cells.
  • Implemented on an FPGA-based testbed with finite-state machine control.
  • Utilized a 1-LSB termination rule and bounded iterations (Nmax=10) for stable runtime.
  • Achieved a normalized mean absolute error of 1.6% over charge and discharge cycles.
  • Synthesis for Artix-7 XC7A100T utilized only 504 LUTs (0.79%) and 580 FFs (0.46%).
  • Successful TSMC 28 nm MPW implementation shown for chip-level integration.

Abstract

State of charge (SOC) estimation is a key function in battery management systems (BMSs) because it directly affects safe operation and available energy prediction. In embedded BMS platforms, information from multiple cells must be processed within tight computation and memory budgets. The estimator therefore needs to balance accuracy and implementation cost. This paper presents a lightweight SOC estimation method based on the relationship between open circuit voltage and state of charge (OCV–SOC) in lithium-ion batteries, together with a standalone gauge IP based on finite-state machine (FSM) control. The reference OCV–SOC curve of a commercial 3.7 V lithium-ion cell is approximated by a two-region quadratic model. The IP estimates OCV from the measured terminal voltage with equivalent series resistance (ESR) correction and updates SOC iteratively. To obtain predictable runtime behavior and to suppress oscillatory behavior near convergence, the hardware combines a 1-LSB termination rule with a guard based on a maximum iteration count of Nmax=10. Real-time validation on an FPGA-based battery measurement testbed achieves an overall normalized mean absolute error (NMAE) of 1.6% over charge and discharge data. When synthesized for an Artix-7 XC7A100T, the proposed gauge IP used only 504 LUTs (0.79%) and 580 FFs (0.46%). A TSMC 28 nm MPW implementation further demonstrates feasibility for integration at chip level.

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Cite This Study

Jang et al. (2026) studied this question.

synapsesocial.com/papers/6a0414f679e20c90b4444cc5https://doi.org/10.3390/electronics15101994
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