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May 15, 2026IEEE Transactions on Neural Networks and Learning Systems0 citations

SALMON: Self-Adaptive Learning Model on Neuromorphic Hardware

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YCYoung Woon ChoSLS. LeeSKSangbum Kim

Key Points

  • The aim is to introduce and evaluate the SALMON model for on-chip training in neuromorphic hardware settings.
  • Employs SALMON, a self-adaptive learning model utilizing SAnet for large-scale neuromorphic systems.
  • Evaluates performance in CIFAR-10 classification with ResNet architecture across different analog device models.
  • Conducts ablation studies using Grad-CAM analysis to assess digital attention blocks' impact.
  • Achieves a test accuracy of 91.49%, improving 13.1% across different network scales with varying nonidealities.
  • Reduces relative power consumption by approximately 70% during on-chip training with minimized digital component use.

Abstract

Analog in-memory computing (AIMC) is a promising technology for energy-efficient acceleration of deep learning workloads. While significant advancements have been achieved in accelerating on-chip inference, on-chip training has not received as much attention due to the challenges posed by the nonideal characteristics of AIMC. Self-adaptive learning model on neuromorphic hardware (SALMON) is introduced as a novel on-chip training method designed to operate effectively on large-scale neuromorphic computing systems. SALMON leverages a self-adaptive network (SAnet) that integrates an analog backbone network with attachable digital attention blocks to enhance network performance, indirectly addressing hardware nonidealities. The effectiveness of SALMON is demonstrated in CIFAR-10 image classification using the ResNet architecture with three distinct levels of analog device models. Performance trends in test accuracy reach 91.49%, reflecting a 13.1% improvement across network scales with varying nonideality levels. Ablation studies assess the impact and role of digital attention blocks based on Grad-CAM analysis. Finally, application strategies are presented to minimize the use of attachable digital components during on-chip training, significantly reducing relative power consumption by approximately 70% under hardware conditions.

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Cite This Study

Cho et al. (2026) studied this question.

synapsesocial.com/papers/6a06b7a1e7dec685947aa562https://doi.org/10.1109/tnnls.2026.3687785
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