Two-transistor zero-capacitor (2T0C) DRAM has attracted attention as an alternative memory due to its high potential for monolithic 3D integration (M3D). However, conventional 2T0C DRAM consists of four terminals, requiring large contact and peripheral area in the array. Moreover, selective read-out in the array has not been sufficiently addressed, as half-selected cells are susceptible to unintended current. To address this, two types of three-terminal 2T0C DRAM, bit-line-shared (BLS) and word-line-shared (WLS), were implemented, together with an offset bias scheme that enables selective read by applying complementary biases to the read terminals. Both structures exhibited retention times exceeding 800 s, comparable to conventional 2T0C DRAM. Array-level read selectivity and sensing margin were evaluated through SPICE simulations under various parasitic capacitance and offset bias conditions. Under optimized conditions, read selectivity values of 1.63 × 105 and 1.51 × 105 were achieved for the BLS and WLS structures, respectively. Notably, the WLS structure exhibited a selected cell on-current of approximately 0.17 μA, one order of magnitude higher than that of the BLS structure. This on-current advantage is analytically attributed to the structural decoupling of write-induced VSN drop and read-induced VGS enhancement in the WLS configuration. These results establish the WLS three-terminal 2T0C DRAM with the offset bias scheme as a more favorable configuration for high-density array implementation.
Kim et al. (Mon,) studied this question.