Introduction/ Objective: In this study, a Forced Leakage Reduction Technique (FLRT) is proposed to minimize leakage power while preserving correct logic operation. Methods: The detailed simulation has been carried out using the Cadence Virtuoso tool at the 45nm technology node. The SRAM characteristics parameters, such as dynamic power, leakage power, delay, Power-Delay Product (PDP), and stability, are determined for the proposed FLRT structure and for all other reported leakage-reduction techniques, including LECTOR, Sleepy Stack, GALEOR, All NMOS Leakage Feedback with Data Retention (ANLFDR), and Tri-mode Power Gating. All analyses are performed by varying the supply voltages from 0.6V to 1V. To perform a fair comparison, all the techniques are simulated at the same technology node. Results: In the proposed FLRT structure, leakage power is reduced by 2.31×, 2.27×, 1.86×, 2.13×, 2.75×, and 2.31×, respectively, compared to 2-input NAND gate, LECTOR, Sleepy Stack, GALEOR, ANLFDR, and Tri-mode Power Gating at 1V. Furthermore, the proposed FLRT structure shows a slightly higher SNM than all other considered techniques. The proposed FLRT structure consumes less dynamic power than the 2-input NAND, LECTOR, ANLFDR, and Tri-mode Power Gating techniques. However, the other two techniques, Sleepy like Stack and GALEOR, consume less power than the FLRT structure. Discussion: The proposed FLRT structure consumes the lowest leakage power among all other considered techniques. It happens due to the presence of leakage-controlled transistors. Out of the two leakage-controlled transistors, one remains in nearly cut-off mode and breaks the path between the supply voltage and ground. FLRT offers a favorable reduction in leakage power with almost the same stability. However, a delay increase has been observed compared to other considered techniques. Conclusion: The proposed FLRT structure may be the most applicable for low-power circuits.
Mittal et al. (Mon,) studied this question.