A 2×32-Gb/s, 128-Gb/s/mm Distributed Single-Ended Transimpedance Amplifier in 28-nm CMOS

This paper presents a 2 × 32 Gb/s 128-Gb/s/mm single-ended distributed transimpedance amplifier fabricated in a 28-nm CMOS processing technology. To address the area-bandwidth trade-off inherent in conventional distributed amplifiers, a distributed biasing scheme is proposed to eliminate large passive terminations and their associated layout overhead. In addition, a dual m-derived inductor-peaking technique is introduced to extend the bandwidth without channel width penalty. The prototype achieves a per-channel data rate of 32-Gb/s, a 3-dB bandwidth of 24 GHz, a transimpedance gain of 42.9 dBΩ, and an edge bandwidth density of 128 Gb/s/mm.