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June 5, 20260 citationsOpen Access

NeuronFabric: A Software Reference Architecture for On-Chip Transformer Training with Local Adam

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EUEvgeny Ukladchikov

Key Points

  • This paper aims to integrate gradient computation and optimizer state updates into a single process for on-chip training.
  • Developed a C# software prototype for a transformer model.
  • Trained a 334K parameter autoregressive transformer on the Shakespeare corpus with Adam updates.
  • Introduced BF16W for efficient weight storage to optimize SRAM usage.
  • Achieved evaluation loss of 1.5426 with BF16W after 80K samples, closely matching GPU FP32 oracle loss of 1.5224.
  • BF16W reduces memory requirement from 4.0 MB to 3.34 MB, providing 660KB additional SRAM headroom.
  • The implementation establishes a foundation for future FPGA/ASIC architecture developments.

Abstract

To our knowledge, publicly documented accelerator architectures generally separate trainingcompute from optimizer state updates or rely on external memory/host orchestration. Inferenceonly chips (Groq LPU, Apple ANE, IBM NorthPole) do not support on-chip gradient computation;training accelerators (Cerebras, Tenstorrent) perform the weight update off-chip. Publiclydocumented training systems generally separate gradient computation from optimizer-statestorage or orchestration.This paper describes an attempt to fix that. We built a complete C# software prototype of atransformer that runs forward pass, backpropagation, and Adam weight update entirely in oneprocess with no external framework. The purpose is to establish that the math works and thenumbers are right, before committing to silicon.The model we trained is a 334K parameter autoregressive transformer (d=88, H=4 heads,f=264, L=4 layers, vocab= 256) trained on the Shakespeare corpus. The BF16W variant reacheseval loss 1.5426 within 80K samples (GPU FP32 oracle: 1.5224), with coherent character-leveltext generation confirmed.We also introduce BF16W: storing weights in BF16 while keeping Adam moments in FP32.For the target FPGA budget, BF16W becomes practically necessary to leave SRAM headroomfor activations. A 334K FP32 model with Adam moments requires 4.0 MB — exactly theZCU102 BRAM limit, leaving zero headroom for activation buffers. With BF16W it requires3.34 MB, leaving 660KB free.We describe the vocabulary-budget constraint we discovered during earlier experiments,quantify the BF16W SRAM saving, and lay out the FPGA training target as the next step. NoFPGA measurements are included in this paper; FPGA implementation and measurement areleft for future work.Code: github.com/Binoculars-X/neuro-fabric (release v1.1.0, commit e9ab47a).Publication purpose: This paper serves as a public architectural disclosure and softwarereference implementation for future FPGA/ASIC implementations of the NeuronFabric system,establishing prior art for the local Adam update architecture. NeuronFabric is a researchprototype and not a production accelerator

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Cite This Study

Evgeny Ukladchikov (2026) studied this question.

synapsesocial.com/papers/6a2269c9763171746d548641https://doi.org/10.5281/zenodo.20529107
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