Stereo matching constitutes a critical technology in applications such as autonomous driving and robot navigation. Conventional algorithms, however, often encounter limitations in real-time performance and resource efficiency when deployed on embedded platforms. This paper presents a real-time stereo matching system implemented on a Field-Programmable Gate Array (FPGA), which is built around a lightweight, hardware-optimized dual-path Semi-Global Matching (SGM) algorithm. The proposed method simplifies the traditional eight-path cost aggregation into horizontal and vertical dual-path aggregation, substantially reducing hardware resource consumption while preserving matching accuracy. The system employs a pipelined architecture that integrates image capture, DDR3 caching, and HDMI display output. Experimental results demonstrate that under the configuration of a 5 × 5 matching window and a disparity range of 64, the system generates stable disparity maps at 60 frames per second, with total power consumption below 2.2 W and FPGA core logic utilization under 30%. Compared to the conventional eight-path SGM, the dual-path strategy incurs only a marginal 6% increase in average bad pixel rate on standard stereo datasets while reducing Block RAM (BRAM) usage by approximately 30%. This achieves an effective practical balance between accuracy, computational efficiency, and power consumption.
Song et al. (2026) studied this question.