Optimizing Digital Systems Implemented in FPGA Through Effective Description of Finite State Machines

In digital systems, finite state machines (FSMs) play a crucial role as controllers, control units, and independent sequential circuits. To efficiently implement these FSMs on advanced hardware platforms such as field-programmable gate arrays (FPGAs), it is essential to represent each FSM in a hardware description language (HDL). This article introduces innovative methods for describing FSMs in Verilog (SystemVerilog) HDL to significantly optimize both the area and performance of synthesized FSM circuits. The presented approach selects the optimal default values for the transition and output functions of an FSM and uses blocking assignment statements to assign these values to variables. This method provides an additional level of optimization independent of the techniques used to improve the FSM during the earlier design stages. Experimental studies on FSM benchmarks show that using this approach with the Quartus design tool reduces the average area of FSMs by approximately 2, and in some cases by up to 6.2. In addition, the average performance of FSMs improves by approximately 2 times and, in some examples, by more than 4 times.