Incremental Pulse-Width Erase (IPWE) Scheme for Fast and Variation-Tolerant GIDL Erase of 3D NAND Flash

In this work, we propose an incremental pulse-width erase (IPWE) scheme for fast and variation-tolerant gate-induced drain leakage (GIDL) erase of 3D NAND flash. For the GIDL erase operation, GIDL-generated hole accumulation is required to raise the channel potential. This requirement leads to a transient state that degrades erase speed and broadens distribution of the erased Vth. In addition, the degradation becomes more pronounced with critical-dimension (CD) variation and temperature variation. The proposed IPWE scheme increases erase pulse width progressively, rather than increasing erase voltage as in the conventional incremental step pulse erase (ISPE) scheme. Sentaurus TCAD simulations of a 3D NAND flash with a surrounded BL PAD structure demonstrate that the IPWE scheme achieves a 1.18 V larger Vth shift compared to the ISPE scheme for the same total erase time of 6.6 ms. The IPWE scheme also effectively narrows the erase Vth shift distribution, reducing it by 40 mV under a 55 nm CD variation, 0.26 V for a 10 nm CD variation between channel strings, and 2 V across a 50 K temperature variation, all within a total erase time of 6.6 ms.