Low-Power CMOS Architecture for Dyslexia Prediction with CLSI-Based Screening Indicators

Early identification of dyslexia is crucial for timely educational intervention; however, conventional screening methods are often subjective, resource-intensive, and unsuitable for large-scale deployment. This work proposes a low-power CMOS-based architecture for dyslexia prediction using CLSI-based screening indicators integrated with machine learning (ML) and deep learning (DL) models. Clinically relevant features—including phonological awareness, rapid automatized naming, spelling consistency, reading fluency, and cognitive-linguistic stress indicators derived from CLSI-aligned assessments—are pre-processed and optimized for hardware-efficient inference. A hybrid ML–DL framework combining Random Forest for feature discrimination and a lightweight CNN-BiGRU network for temporal–linguistic pattern learning is mapped onto an energy-efficient CMOS datapath optimized using voltage scaling and clock gating. Experimental evaluation on a benchmark dyslexia screening dataset comprising 1,200 student records demonstrates a prediction accuracy of 96.8%, precision of 95.9%, recall of 97.4%, and F1-score of 96.6%, outperforming conventional software-only implementations by 4–7%. Hardware synthesis results using a 65-nm CMOS technology show a 38% reduction in power consumption and 31% lower inference latency compared to baseline CMOS ML accelerators, while operating at 0.9 V with an average energy consumption of 0.42 mJ per prediction. The proposed architecture enables reliable, real-time, and scalable dyslexia screening suitable for school-level edge devices and portable diagnostic systems, bridging clinical screening standards with low-power intelligent hardware design.