SAT-inspired feature engineering with stacking ensemble learning for fault detection in digital logic circuits

Fault detection in Digital Logic Circuits is an important problem in Very Large Scale Integration (VLSI) testing especially in case of growing circuit complexity and various fault characteristics. Traditional methods tend to have a problem in the ability to accurately classify the faults with different levels of difficulty. This paper presents a new framework that combines attack inspired features from Boolean Satisfiability (SAT) with deep learning ensemble learning algorithms for holistic fault detection classification. The paper proposes a suite of novel features that are based on the SAT solver mechanics such as backtrack estimation, miter circuit complexity, distinguishing input patterns, controllability and observability metrics, and test pattern generation complexity indicators. These features represent the complex relationships between circuit structure and the fault detectability that is not modeled by these conventional approaches. The proposed stacking ensemble architecture employs Random Forest, XGBoost, LightGBM, CatBoost, Extra Trees and Histogram Gradient Boosting classifiers as its first level classifiers and a meta-learner to obtain the best classifier results. Extensive experimentation of benchmark circuits shows incredible results: 99.13% test accuracy, 99.15% precision, 99.18% recall and 99.13% F1-Score. The proposed framework performs better compared to individual state-of-the-art models by 2.66% and shows an exceptional stability with minimal overfitting gap of 0.49%. Cross validation analysis is used to verify the performance consistency (99.15% ± 0.78%) and accuracy for each class performance reaches 100%, 98.8%, and 98.5% for easy faults, medium complexity faults, and challenging faults, respectively. The results confirm the effectiveness of SAT-inspired features and advanced ensemble learning for reliable and scalable fault detection classification.